1. Field
Exemplary embodiments of the present invention relate to an integrated circuit and a memory device, and more particularly, to a technology for transmitting data stored in a nonvolatile memory in an integrated circuit or memory device to numerous parts of the integrated circuit or memory device.
2. Description of the Related Art
FIG. 1 is a diagram for illustrating a repair operation of a conventional memory device.
Referring to FIG. 1, the conventional memory device includes a cell array 110, a row circuit 120, and a column circuit 130. The cell array 110 includes a plurality of memory cells. The row circuit 120 is configured to enable a word line selected by a row address R_ADD. The column circuit 130 is configured to access (read or write) data of a bit line selected by a column address C_ADD.
A row fuse circuit 140 is configured to store a row address, corresponding to a memory cell having a defect in the cell array 110, and generate a repair row address REPAIR_R_ADD. A row comparison unit 150 is configured to compare the repair row address REPAIR_R_ADD stored in the row fuse circuit 140 to the row address R_ADD inputted from an external source. When the repair row address REPAIR_R_ADD coincides with the row address R_ADD, the row comparison unit 150 controls the row circuit 120 to enable a redundant word line instead of the word line designated by the row address R_ADD.
A column fuse circuit 160 is configured to store a column address, corresponding to a memory cell having a defect in the cell array 110, and generate a repair column address REPAIR_C_ADD. A column comparison unit 170 is configured to compare the repair column address REPAIR_C_ADD from the column fuse circuit 160 to the column address C_ADD inputted from an external source. When the repair column address REPAIR_C_ADD coincides with the column address C_ADD, the column comparison unit 170 controls the column circuit 130 to access a redundant bit line, instead of the bit line designated by the column address C_ADD.
The row fuse circuit 140 and the column fuse circuit 160 (hereinafter referred to as the fuse circuits) of FIG. 1 use laser fuses. The laser fuse stores high or low data depending on whether the fuse is cut or not. The laser fuse may be programmed in a wafer state, but may not be programmed after the wafer is mounted in a package. Furthermore, the laser fuse may not be designed small, because of a pitch limit. To overcome such a design difficulty, an E-fuse may be used. The E-fuse may include a transistor or capacitor and/or resistor. When the E-fuse includes a transistor, the E-fuse stores data by changing resistance between a gate and a drain/source.
FIG. 2 is a diagram illustrating that the E-fuse including a transistor operates as a resistor or capacitor.
Referring to FIG. 2, the E-fuse includes a transistor T. When a normal power supply voltage, which the transistor T may tolerate, is supplied to a gate G, the E-fuse operates as a capacitor C. Therefore, there is no current flowing between the gate G and a drain D or source S (hereinafter referred to as a drain-source D-S). However, when a high voltage, which the transistor T may not tolerate, is supplied to the gate G, gate oxide of the transistor T may become inoperable to short the gate G and the drain-source D-S. In this case, the E-fuse operates as a resistor R. Therefore, a current flows between the gate G and the drain-source D-S.
Such a characteristic may be used to recognize the data of the E-fuse through the resistance value between the gate G and the drain-source D-S of the E-fuse. To recognize the data of the E-fuse, (1) the size of the transistor T may be increased to directly recognize the data without a separate sensing operation, or (2) an amplifier may be used to sense a current flowing in the transistor T without increasing the size of the transistor T. In the above-described two methods, however, the transistor T forming the E-fuse must be enlarged, or the amplifier for amplifying data must be provided for each E-fuse. Therefore, both methods have limitations and concerns over the size and space.
Because of the above-described concerns related to the size and space, it may not be easy to apply the E-fuse to the fuse circuits 140 and 160 of FIG. 1. Therefore, as disclosed in U.S. Pat. Nos. 6,904,751, 6,777,757, 6,667,902, 7,173,851, and 7,269,047, researches have been conducted on a method for performing a repair operation using data stored in an E-fuse array including a plurality of E-fuses (in this case, the entire area may be reduced because an amplifier is shared).
To use data (for example, repair information) stored in a nonvolatile memory, such as an E-fuse array, provided in a memory device, a boot-up operation must be performed to transmit the data stored in the E-fuse array to each area of the memory device where the data stored in the E-fuse array is used.